Natarajan Viswanathan

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In this paper, we present <i>FastPlace</i> -- a fast, iterative, flat placement algorithm for large-scale standard cell designs. <i>FastPlace</i> is based on the quadratic placement approach. The quadratic approach formulates the wirelength minimization problem as a convex quadratic program, which can be solved efficiently by some analytical techniques.(More)
In the past few years, there has been a lot of research in the area of global placement. In comparison, not much attention has been paid to the detailed placement problem. Existing detailed placers either fail to improve upon the excellent solution quality enabled by good global placers or are very slow. To handle the above problems, we focus on the(More)
In this paper, we present FastPlace 3.0 - an efficient and scalable multilevel quadratic placement algorithm for large-scale mixed-size designs. The main contributions of our work are: (1) A multilevel global placement framework, by incorporating a two-level clustering scheme within the flat analytical placer FastPlace (Viswanathan and Chu, 2005) and(More)
The last few years have seen significant advances in the quality of placement algorithms. This is in part due to the availability of large, challenging testcases by way of the ISPD-2005 [17] and ISPD-2006 [16] placement contests. These contests primarily evaluated the placers based on the half-perimeter wire length metric. Although wire length is an(More)
This paper describes a simple and effective quadratic placement algorithm called <i>RQL.</i> We show that a good quadratic placement, followed by local wirelength-driven spreading can produce excellent results on large-scale industrial ASIC designs. As opposed to the current top performing academic placers [4, 7, 11], <i>RQL</i> does not embed a(More)
We propose a new multilevel framework for large-scale placement called MAPLE that respects utilization constraints, handles movable macros and guides the transition between global and detailed placement. In this framework, optimization is adaptive to current placement conditions through a new density metric. As a baseline, we leverage a recently developed(More)
Existing routability-driven placers mostly employ rudimentary and often crude congestion models that fail to account for the complexities in modern designs, e.g., the impact of non-uniform wiring stacks, layer directives, partial and/or complete routing blockages, etc. In addition, they are hampered by congestion metrics that do not accurately score or(More)
The impact of considering design hierarchy during physical synthesis remains a fairly under-researched area. This is especially true for large-scale circuit placement. This is in large part due to the non-availability of realistic public designs with the design hierarchy information. Additionally, modern designs are fairly complex with numerous placement(More)
Modern designs often contain a combination of a large number of standard cells and macro blocks. Traditionally large macro blocks are handled at the floorplanning level, after which their positions are fixed. The standard cells are then handled during the placement level. Current designs can have hundreds of large and medium sized macro blocks and a large(More)
Circuit performance is greatly affected by the quality and optimization metrics of placement algorithms. At modern technology nodes, improving routability and reducing total wirelength are no longer sufficient to <i>close timing</i>, as nets may require specialized attention to reduce <i>negative slack</i>. To this end, <i>incremental timing-driven(More)