Narender Hanchate

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In CMOS circuits, the reduction of the threshold voltage due to voltage scaling leads to increase in subthreshold leakage current and hence static power dissipation. We propose a novel technique called LECTOR for designing CMOS gates which significantly cuts down the leakage current without increasing the dynamic power dissipation. In the proposed(More)
The continuous scaling trends of interconnect wires in deep submicron (DSM) circuits result in increased interconnect delay and crosstalk noise. In this work, we develop a new postlayout gate sizing algorithm for simultaneous optimization of interconnect delay and crosstalk noise. The problem of postlayout gate sizing is modeled as a normal form game and(More)
In this paper, we propose a new methodology for wire sizing with simultaneous optimization of interconnect delay and crosstalk noise in deep submicron VLSI circuits. The wire sizing problem is modeled as an optimization problem formulated as a normal form game and solved using the Nash equilibrium. Game theory allows the optimization of multiple metrics(More)
In this paper, a new tool CHESS, is designed and developed for control and data-flow graph (CDFG) extraction and the high level synthesis of low power designs from behavioral level VHDL descriptions. The tool optimizes latency, area and power during the different phases of synthesis and provides several solutions to evaluate the trade-offs during design.(More)
In CMOS circuits, the reduction of the threshold voltage due to voltage scaling leads to increase in sub threshold leakage current and hence, static power dissipation. We propose a novel technique called LECTOR for designing CMOS gates which significantly cuts down the leakage current without increasing the dynamic power dissipation. In the proposed(More)
In this paper, we develop a new post-layout gate sizing algorithm for simultaneous optimization of interconnect delay and crosstalk noise. We have modeled the problem of gate sizing as a normal form game and solved using the Nash equilibrium. The noise induced on a net depends on the size of the gates driving the coupled nets and itself. Increasing the gate(More)
The continuous scaling of interconnect wires in deep submicron (DSM) circuits results in increased interconnect delay, power, and crosstalk noise. In this work, we develop a game-theoretic framework and multimetric optimization algorithms for the simultaneous optimization during wire sizing of (i) interconnect delay and crosstalk noise, and (ii)(More)
The aggressive scaling of technology parameters in deep submicron (DSM) circuits has led towards an increased impact of process variations on delay and crosstalk noise. In this work, we develop a new post-layout gate sizing algorithm for simultaneous reduction of delay uncertainty and crosstalk noise under the impact of process variations. The problem of(More)
The crosstalk noise induced on a net depends on its wire size, its driver size and the sizes of the aggressor gates driving its coupled nets. The problem of crosstalk noise optimization at post-route level is difficult due to the cyclic dependency on aggressor and victim driver sizes, resulting in a conflicting situation. Game theory provides a natural(More)
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