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Crossbar arrays based on two-terminal resistive switches have been proposed as a leading candidate for future memory and logic applications. Here we demonstrate a high-density, fully operational hybrid crossbar/CMOS system composed of a transistor- and diode-less memristor crossbar array vertically integrated on top of a CMOS chip by taking advantage of the(More)
Ultra-low energy biologically-inspired neuron and synapse integrated circuits are presented. The synapse includes a spike timing dependent plasticity (STDP) learning rule circuit. These circuits have been designed, fabricated and tested using a 90 nm CMOS process. Experimental measurements demonstrate proper operation. The neuron and the synapse with STDP(More)
Efficiently passing spiking messages in a neural model is an important aspect of high-performance simulation. As the scale of networks has increased so has the size of the computing systems required to simulate them. In addition, the information exchange of these resources has become more of an impediment to performance. In this paper we explore spike(More)
In this paper, we describe a new method for visual recognition of objects in an image that combines feature-based object classification with efficient search mechanisms based on swarm intelligence. Our approach utilizes the particle swarm optimization algorithm (PSO), a population based evolutionary algorithm, which is effective for optimization of a wide(More)
We address the problem of computing immobilizing xtures and grasps of three-dimensional objects, using simple xturing devices and grippers with both discrete and continuous degrees of freedom. The proposed approach is based on the notion of second-order immobility introduced by Rimon and Burdick 48, 49, 50], which is used here to derive simple suucient(More)
This paper addresses the problem of grasping and manipulating three-dimensional objects with a reconngurable gripper equipped with two parallel plates whose distance can be adjusted by a computer-controlled actuator. The bottom plate is a bare plane, and the top one carries a rectangular grid of actuated pins that can translate in discrete increments under(More)
In this paper, we describe the design of an artificial neural network for spatiotemporal pattern recognition and recall. This network has a five-layered architecture and operates in two modes: pattern learning and recognition mode, and pattern recall mode. In pattern learning and recognition mode, the network extracts a set of topologically and temporally(More)
The design and simulation of a scalable neural chip with synaptic electronics using nanoscale memristors fully integrated with complementary metal-oxide-semiconductor (CMOS) is presented. The circuit consists of integrate-and-fire neurons and synapses with spike-timing dependent plasticity (STDP). The synaptic conductance values can be stored in memristors(More)
Modeling of large-scale spiking neural models is an important tool in the quest to understand brain function and subsequently create real-world applications. This paper describes a spiking neural network simulator environment called HRL Spiking Simulator (HRLSim). This simulator is suitable for implementation on a cluster of general purpose graphical(More)