Naran Sirisantana

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—In this paper, we present a noise-tolerant high-performance static circuit family suitable for low-voltage operation called skewed logic. Skewed logic circuits in comparison with Domino logic have better scalability and they are more suitable for low voltage applications because of better noise margins. Skewed logic and its variations have been compared(More)
In very high performance designs, dynamic circuits, such as Domino Logic, are used because of their high speed. Skewed logic circuits can be used to achieve designs having performance comparable to that of Domino but with better scalability. Moreover, a selective clocking scheme may be applied to enhance the power savings for skewed logic circuits. This(More)
Skewed logic circuits belong to a noise-tolerant high-performance static circuit family. Skewed logic circuits can achieve performance comparable to that of Domino logic circuits but with much lower power consumption. Two factors contribute to the reduction in power. First, by exploiting the static nature of skewed logic circuits, we can alleviate the cost(More)
This paper proposes Selectively Clocked Logic (SCL) style b sed on skewed logic for noise-tolerant low-power high-performance applications.Variations of the logic style with multiple threshold voltage (MVth-SCL) and multiple oxide thickness (Mtox-SCL) techniques are also studied. Simulation results indicate that SCL, MVth-SCL, and Mtox-SCL circuits reduce(More)
We present an integer linear programming-based approach for solving the logic reconvergence problem in skewed logic circuits with minimal logic duplication cost. A simplification technique is applied to reduce the complexity of the ILP problem greatly so that the run time is more affordable. Experimental results show that an average of 18% of original gates(More)
In very high performance designs, dynamic circuits, such as Domino Logic, are used because of their high speed. Skewed logic circuits can be used to achieve designs having performance comparable to that of Domino but with better scalability. Moreover, a selective clocking scheme may be applied to enhance the power savings for skewed logic circuits. This(More)
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