Naoki Fujieda

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With the rapid advances in semiconductor process technology and microarchitecture, the speed gap between the clock cycle time of processor cores and that of memory systems has increased significantly. To solve this problem, memory system should be efficiently managed. In general, since a thread with fewer requests has a large capability to improve the total(More)
Oblivious RAM (ORAM) is a technique to hide the access pattern of data to untrusted memory along with their contents. Path ORAM is a recent lightweight ORAM protocol, whose derived access pattern involves some redundancy that can be removed without the loss of security. In this paper, we introduce last path caching, which removes the redundancy of Path ORAM(More)
In this paper, we describe the architecture of MipsCoreDuo, a microprocessor which is designed for LSI Design Contest in Okinawa 2009. MipsCoreDuo is a multifunction dual-core processor that has four attractive execution modes. It achieves high-parallel performance, high-sequential performance or high-dependability with single design. We implemented it in(More)
Instruction set randomization (ISR), which modifies or enhances instruction coding of processors, is one of the cost-effective techniques to obfuscate embedded software. Using an Instruction Register File (IRF) for ISR was proposed and explored, while the existing technique lacked a protection against falsification of software. This study presents a(More)
The number of processor cores on a chip tends to increase because of the limitation of single thread performance. For many-core architectures, efficient use of last-level cache (LLC) is important. Recent techniques which have been proposed are core-divided LLC and forward an evicted line from one cache to another cache. In this paper, we propose a new cache(More)
The instruction register file (IRF) is an attractive approach to reduce power consumption, which is essential to many embedded systems. However, the previously proposed IRF implementation is not efficient in merging similar instructions into a single entry in the IRF. In this paper, we propose an XOR-based merging approach that achieves higher efficiency in(More)
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