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- Namrata Shekhar, Sudhakar Kalla, Florian Enescu
- IEEE Transactions on Computer-Aided Design ofâ€¦
- 2007

This paper addresses the equivalence verification problem of register-transfer level (RTL) descriptions that implement arithmetic computations (such as add, mult) over bit vectors with finite widths. A bit vector of size represents integer values from 0 to 2<sup>m</sup>-1, implying that the corresponding integer values are reduced moduloâ€¦ (More)

- Namrata Shekhar, Priyank Kalla, Florian Enescu, Sivaram Gopalakrishnan
- ICCAD-2005. IEEE/ACM International Conference onâ€¦
- 2005

This paper addresses the problem of equivalence verification of RTL descriptions. The focus is on datapath-oriented designs that implement polynomial computations over fixed-size bit-vectors. When the size (m) of the entire datapath is kept constant, fixed-size bit-vector arithmetic manifests itself as polynomial algebra over finite integer rings of residueâ€¦ (More)

- Namrata Shekhar, Priyank Kalla, Florian Enescu
- Proceedings of the Design Automation & Test inâ€¦
- 2006

This paper addresses the problem of equivalence verification of RTL descriptions that implement arithmetic computations (add, mult, shift) over bit-vectors that have differing bit-widths. Such designs are found in many DSP applications where the widths of input and output bit-vectors are dictated by the desired precision. A bit-vector of size n canâ€¦ (More)

- Namrata Shekhar, Priyank Kalla, Sivaram Gopalakrishnan, Florian Enescu
- 2005 International Conference on Computer Design
- 2005

This paper addresses the problem of equivalence verification of high-level/RTL descriptions. The focus is on datapath-oriented designs that implement univariate polynomial computations over fixed-size bit-vectors. When the size (m) of the entire datapath is kept constant, fixed-size bit-vector arithmetic manifests itself as polynomial algebra over finiteâ€¦ (More)

- Neal Tew, Priyank Kalla, Namrata Shekhar, Sivaram Gopalakrishnan
- 2008 IEEE/ACM International Conference onâ€¦
- 2008

This paper addresses the problem of solving finite word-length (bit-vector) arithmetic with applications to equivalence verification of arithmetic datapaths. Arithmetic datapath designs perform a sequence of Add, Mult, Shift, Compare, Concatenate, Extract, etc., operations over bit-vectors. We show that such arithmetic operations can be modeled, asâ€¦ (More)

- Namrata Shekhar, Priyank Kalla, M. Brandon Meredith, Florian Enescu
- IEEE Transactions on Very Large Scale Integrationâ€¦
- 2008

This paper addresses simulation-based verification of high-level [algorithmic, behavioral, or register-transfer level (RTL)] descriptions of arithmetic datapaths that perform polynomial computations over finite word-length operands. Such designs are typically found in digital signal processing (DSP) for audio/video and multimedia applications; where theâ€¦ (More)

- Namrata Shekhar, Priyank Kalla, M. Brandon Meredith, Florian Enescu
- 2006 Formal Methods in Computer Aided Design
- 2006

This paper addresses simulation-based verification of high-level descriptions of arithmetic datapaths. Instances of such designs are commonly found in DSP for audio, video and multimedia applications, where the word-lengths of input/output bit-vectors are fixed according to the desired precision. Initial descriptions of such systems are usually specified asâ€¦ (More)

- M. Brandon Meredith, BRANDON MEREDITH, +5 authors Namrata Shekhar
- 2015

In this thesis we discuss how to find equivalent representations of polynomial functions over the ring of integers modulo a power of a prime. Specifically, we look for lower degree representations and representations with fewer variables for which important applications in electrical and computer engineering exist. We present several algorithms for findingâ€¦ (More)

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