Namiko Ikeda

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Verification of the hardware/software functions of a 10-Gbit/s-class large-scale network systems-on-a-chip (NW SoC) requires the use of multiple field programmable gate array (FPGA) devices. We propose two schemes for the efficient mapping of the design data of the NW SoC into FPGA devices. We implemented practical NW SoC design data for FPGA devices, and(More)
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