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Multi-core processors have become common in current computing platforms. Today, most of multi-core workstations and PCs have adopted NUMA (Non-Uniform Memory Access) advanced memory architecture for high performance and scalability. In response, EDA (Electronic Design Automation) community has applied significant effort to parallelize many EDA algorithms(More)
Traditional parallel event-driven HDL simulation methods suffer heavy synchronization & communication overhead for timely transferring the signal data among local simulators, which could easily nullify most of the expected simulation speed-up from parallelization. A new predictive parallel event-driven HDL simulation as a new promising approach had been(More)
Formal property verification (also known as model checking) is a powerful methodology that can be used to find corner-case bugs, improve verification efficiency and reduce the verification cycle. However, inconclusive formal analysis results or bounded proofs have been hindering adoption of formal technology in the industry. This paper describes a formal(More)
Simulation-based functional verification is characterized by two inherently conflicting targets: the signal visibility and simulation performance. Achieving a proper trade-off between these two targets is of paramount importance. Even though HDL simulators are the most widely used verification platform at the RTL and gate level, their major drawback is the(More)
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