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Monitoring applications at run-time and evaluating the recorded statistical data of the underlying micro architecture is one of the key aspects required by many hardware architects and system designers as well as high-performance software developers. To fulfill this requirement, most modern CPUs for High Performance Computing have been equipped with(More)
Future exascale machines will require multi--/ many-core architectures able to efficiently run multi-threaded applications. Data-flow execution models have demonstrated to be capable of improving execution performance by limiting the synchronization overhead. This paper proposes to augment cores with a minimalistic set of hardware units and dedicated(More)
The trend to develop increasingly more intelligent systems leads directly to a considerable demand for more and more computational power. Programming models that aid to exploit the application parallelism with current multi-core systems exist but with limitations. From this perspective, new execution models are arising to surpass limitations to scale up the(More)
To deploy a memory protection mechanism, it requires CPU support hardware components like Memory Management Unit (MMU) or Memory Protection Unit (MPU). However, in embedded system, most of microcontrollers lack to be equipped these features because they cause the system incurred hardware cost and performance penalty. In this paper, a method to detect memory(More)
The path towards future high performance computers requires architectures able to efficiently run multi-threaded applications. In this context, dataflow-based execution models can improve the performance by limiting the synchronization overhead, thanks to a simple producer-consumer approach. This paper advocates the ISE of standard cores with a small(More)
Recently, application in embedded systems has increasingly become complex. This requires having tools to prevent or detect memory corruption errors during the software development process. Unfortunately, most of embedded processors lack to be equipped a MMU (Memory Management Units), one of hardware components supporting memory protection mechanism in(More)
Ahstract-This paper presents the first steps towards the im­ plementation of an evolvable and self-adaptable processor cache. The implemented system consists of a run-time reconfigurable memory-to-cache address mapping engine embedded into the split level one cache of a Leon3 SPARe processor as well as of an measurement infrastructure able to profile(More)
Related work has presented simulation-based experiments to classify data accesses in a shared memory multi-core into private and shared. This information can be used to selectively turn on/off cache coherency mechanisms for data blocks, which can save memory bus bandwidth, minimize energy consumption, and reduce application runtimes. In this paper we(More)
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