Nak-Woong Eum

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Temperature monitoring using thermal sensors is an essential tool for evaluating the thermal behavior and sustaining the reliable operation in high-performance and high-power systems. With current technology scaling and integration trends timely and accurate detection of localized heating will be evermore important. In this work, we address the creation of(More)
This paper presents a new performance and routability driven routing algorithm for symmetrical array based field-programmable gate arrays (FPGAs). A key contribution of our work is to overcome one essential limitation of the previous routing algorithms: <i>inaccurate estimations of routing density</i> which were too general for symmetrical FPGAs. To this(More)
This paper describes a system on chip (SoC) implementation of terrestrial digital multimedia broadcasting (T-DMB) receiver which integrates RF tuner, analog to digital converter (ADC), baseband processor, and multimedia processor in single silicon wafer. The pseudo-SRAM (PSRAM) and SDRAM are doubly stacked with method of silicon in package (SIP). A low-IF(More)
The advancement of process technology enables the integration of multiple cores featuring parallel processing. The requirement of extensive memory bandwidth puts a major performance bottleneck in multi-core architectures for media applications. While the parallel memory system is a viable solution to account for a large amount of memory transactions(More)
The TETRA (terrestrial trunked radio) speech codec is mandatory for all TETRA mobiles and networks. This paper presents the cost-effective implementation of the TETRA speech codec using the primitive functions of the compiler for the 16 bit fixed-point eDSP (embedded DSP), which was developed by ETRI for the purpose of use in various SoCs. Generally, the(More)
In this paper, an efficient hardware architecture that exploits parallel processing for HEVC decoders is proposed by introducing (i) a Coding Tree Unit (CTU)-level pipelined architecture for single-core based processing; and (ii) a multi-core based parallel processing architecture for picture partition decoding with low latency while not requiring(More)