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Architecting voltage islands in core-based system-on-a-chip designs
TLDR
We define the problem of architecting voltage islands in core-based designs and present a new algorithm for simultaneous voltage island partitioning, voltage level assignment and physical-level floorplanning. Expand
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A power estimation methodology for systemC transaction level models
TLDR
We present a methodology for performing system level power estimation for different scenarios or applications being executed on SystemC transaction level models. Expand
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Temperature-aware voltage islands architecting in system-on-chip design
TLDR
We present a hybrid optimization approach which aims at temperature reduction and hot spot elimination for system-on-chip designs. Expand
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Exploring power management in multi-core systems
TLDR
This paper presents a performance and power analysis methodology for multi-core systems that can be easily reconfigured for different scenarios and a PM infrastructure for the exploration and analysis of PM algorithms. Expand
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Leakage Power Contributor Modeling
TLDR
This paper describes an alternative “power contributor”based approach to cell leakage characterization that exploits inherent separability of power consumption for different portions of a cell. Expand
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Transaction level error susceptibility model for bus based SoC architectures
TLDR
System on Chip architectures have traditionally relied upon bus based interconnect for their communication needs. Expand
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Behavioral synthesis of analog systems using two-layered design space exploration
TLDR
This paper presents a novel approach for synthesis of analog systems from behavioral VHDL-AMS specifications. Expand
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Hierarchical constraint transformation using directed interval search for analog system synthesis
TLDR
In this paper, we present a hierarchical approach for constraint transformation. Expand
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Transaction-level modeling for architectural and power analysis of PowerPC and CoreConnect-based systems
TLDR
This paper presents the transaction-level models developed at IBM for PowerPC and CoreConnect-based systems. Expand
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A two-layer library-based approach to synthesis of analog systems from VHDL-AMS specifications
TLDR
This paper presents a synthesis methodology for analog systems described using VHDL-AMS language. Expand
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