Nagi N. Mekhiel

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Neither simulation results nor real system results give an explanation to the behavior of advanced computer systems for the full design spectrum. In this paper, we present simple models that explain the behavior of simultaneous multithreded, multiprocessor and multiprocessor with simultaneous multithreaded architectures. The results of these models show(More)
Spatial and temporal localities used in keeping references in cache is limited by the behavior of applications. Many applications that lack these localities, and have high frequency of use of accesses results in a degradation of system performance under the conventional cache design. The proposed method, tracks most frequently used references by dynamically(More)
Multi-Level Processing reduces the cost of synchronization overhead with an upper level processor for taking control and issuing the right to use shared data and to enter critical sections directly to each of lower level processors at processor speed. The instruction registers of lower level parallel processors are mapped to the data memory of upper level(More)
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