Nagaraju Pothineni

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Performance of an application can be improved through augmenting the processor with application specific functional units (AFUs). Usually a cluster of operations identified from the application forms the behavior of an AFU. Several researchers studied the impact of input and output (I/O) constraints for a legal operation cluster on the overall achievable(More)
Custom instruction set extensions (ISEs) are added to an extensible base processor to provide application-specific functionality at a low cost. As only one ISE executes at a time, resources can be shared. This paper presents a new high-level synthesis flow targeting ISEs. We emphasize a new technique for resource allocation, binding, and port assignment(More)
Today’s customizable processors allow the designer to augment the base processor with custom accelerators. By choosing appropriate set of accelerators, designer can significantly enhance the performance and power of an application. Due to the large number of accelerator choices and their complex trade-offs among reuse, gain and area, manually deciding the(More)
In the automatic design of custom instruction set processors, there can be a very large set of potential custom instructions, from which a few instructions are required to be chosen, taking into account their spatial as well as temporal reuse and cost. Using the existing pattern matching techniques, finding complete reuse of every identified pattern in the(More)
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