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Ultra-scaled FinFET transistors bear unique fingerprint-like device-to-device differences attributed to random single impurities. Through correlation of experimental data with multimillion atom simulations in NEMO 3-D, we can identify the impurity's chemical species and determine their concentration, local electric field and depth below the Si/SiO 2(More)
—The noise in n-channel bulk MuGFETs with 2.5 nm SiON gate dielectric is reported. It is shown that besides number fluctuations-related 1/f noise often Generation-Recombination (GR) noise is observed. From a detailed study of the fin length and width dependence it is concluded that the GR noise preferentially occurs for short and wide transistors. The(More)
  • Vaidy Subramanian, Bertrand Parvais, Jonathan Borremans, Abdelkarim Mercha, Dimitri Linten, Piet Wambacq +13 others
  • 2006
—Comparison of digital and analog figures-of-merit of FinFETs and planar bulk MOSFETs reveals an interesting trade-off in the analog/RF design space. It is found that FinFETs possess the following key advantages over bulk MOSFETs: reduced leakage , excellent subthreshold slope, and better voltage gain without degradation of noise or linearity. This makes(More)
We report the observation of lifetime-enhanced transport (LET) based on perpendicular valleys in silicon by transport spectroscopy measurements of a two-electron system in a silicon transistor. The LET is manifested as a peculiar current step in the stability diagram due to a forbidden transition between an excited state and any of the lower energy states(More)
The investigation of complex communication in cellular networks requires superior measurement tools than those available to date. Electrode arrays integrated onto silicon electronics are increasingly used to measure the electrical activity of cells in an automated and highly parallelized fashion, but they are restricted to recording extracellular(More)
Channel conductance measurements can be used as a tool to study thermally activated electron transport in the sub-threshold region of state-of-art FinFETs. Together with theoretical Tight-Binding (TB) calculations, this technique can be used to understand the evolution of source-to-channel barrier height (E b) and of active channel area (S) with gate bias(More)
  • Giuseppe Carlo Tettamanzi, Abhijeet Paul, Sunhee Lee, Saumitra R Mehrotra, Nadine Collaert, Giuseppe Tettamanzi +10 others
  • 2014
The presence of interface states at the MOS interface is a well-known cause of device degradation. This is particularly true for ultra-scaled FinFET geometries where the presence of a few traps can strongly influence device behavior. Typical methods for interface trap density (Dit) measurements are not performed on ultimate devices, but on custom designed(More)