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Ultra-scaled FinFET transistors bear unique fingerprint-like device-to-device differences attributed to random single impurities. Through correlation of experimental data with multimillion atom simulations in NEMO 3-D, we can identify the impurity's chemical species and determine their concentration, local electric field and depth below the Si/SiO 2(More)
Channel conductance measurements can be used as a tool to study thermally activated electron transport in the sub-threshold region of state-of-art FinFETs. Together with theoretical Tight-Binding (TB) calculations, this technique can be used to understand the evolution of source-to-channel barrier height (E b) and of active channel area (S) with gate bias(More)
The investigation of complex communication in cellular networks requires superior measurement tools than those available to date. Electrode arrays integrated onto silicon electronics are increasingly used to measure the electrical activity of cells in an automated and highly parallelized fashion, but they are restricted to recording extracellular(More)
  • Giuseppe C Tettamanzi, Abhijeet Paul, Gabriel P Lansbergen, Jan Verduijn, Sunheee Lee, Abhijeet Paul +11 others
  • 2014
—Thermally activated subthreshold transport has been investigated in undoped triple-gate MOSFETs. The evolution of the barrier height and of the active cross-sectional area of the channel as a function of gate voltage has been determined. The results of our experiments and of the tight-binding simulations we have developed are both in good agreement with(More)
The presence of interface states at the MOS interface is a well-known cause of device degradation. This is particularly true for ultra-scaled FinFET geometries where the presence of a few traps can strongly influence device behavior. Typical methods for interface trap density (Dit) measurements are not performed on ultimate devices, but on custom designed(More)
In this work, we will review the current progress in integration and device design of high mobility devices. With main focus on (Si)Ge for PMOS and In(Ga)As for NMOS, the benefits and challenges of integrating these materials on a Si platform will be discussed for both density scaling (" more Moore ") and functional scaling to enhance on-chip functionality(More)