Nadine Azémard

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—The logical effort method is widely recognized as a pedagogical way allowing designers to quickly estimate and optimize single paths by modeling equivalently propagation delay and transition time. However, this method necessitates a calibration of all the gates of the library and appears suboptimal in real combi-natorial paths for satisfying tight timing(More)
Using explicit modeling of delays, we present and discuss real design conditions of CMOS buffers from the viewpoint of power dissipation. Efficiency of buffer implementation is first studied through the definition of limit for buffer insertion. Closed form alternatives to the design for minimum power-delay product are then proposed in terms of this limit.(More)
For supply voltage standards such as Vdd > V TN + |V TP | short–circuit power dissipation significantly contributes to the total power dissipation in ICs. We propose a new alternative for the estimation of the short–circuit power dissipation, Psc, in CMOS structures. A first order calculation results in an explicit formulation for Psc, which clearly shows(More)
In this paper we present a local strategy for sizing CMOS circuits. We show how the explicit definition of delays can be used to define delay/area optimal sizing rules. Examples are given for sizing irregular inverter arrays, NAND gates and adder cells, starting from an initial electrical netlist and ending with the fully automatically generated layout.(More)