Nadine Azémard

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The logical effort method is widely recognized as a pedagogical way allowing designers to quickly estimate and optimize single paths by modeling equivalently propagation delay and transition time. However, this method necessitates a calibration of all the gates of the library and appears suboptimal in real combinatorial paths for satisfying tight timing(More)
This article aims at highlighting new design issues coming from the increasing sensitivity of digital circuits towards process variability. CAD tools and current design methodologies are not anymore efficient to tackle such aspects. In particular variability is increasing the difficulty to identify setup and hold time violations. This paper is a study of(More)
In the nanometer era, the physical verification of a CMOS digital circuit becomes a long, tedious, and complex task. Designers must indeed account for numerous new factors that impose a drastic change in validation and physical-verification methods. One of these major changes in timing verification to handle process variation lies in the progressive(More)
Using explicit modeling of delays, we present and discuss real design conditions of CMOS buffers from the viewpoint of power dissipation. Efficiency of buffer implementation is first studied through the definition of limit for buffer insertion. Closed form alternatives to the design for minimum power-delay product are then proposed in terms of this limit.(More)
For supply voltage standards such as Vdd > V TN + |V TP | short–circuit power dissipation significantly contributes to the total power dissipation in ICs. We propose a new alternative for the estimation of the short–circuit power dissipation, Psc, in CMOS structures. A first order calculation results in an explicit formulation for Psc, which clearly shows(More)