Nader Bagherzadeh

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ÐThis paper introduces MorphoSys, a reconfigurable computing system developed to investigate the effectiveness of combining reconfigurable hardware with general-purpose processors for word-level, computation-intensive applications. MorphoSys is a coarse-grain, integrated, and reconfigurable system-on-chip, targeted at high-throughput and data-parallel(More)
Hartej Singh, Ming-Hau Lee, Guangming Lu, Fadi J. Kurdahi, Nader Bagherzadeh, University of California, Irvine, CA 92697 and Eliseu M. C. Filho, Federal University of Rio de Janeiro, Brazil Abstract: This paper introduces MorphoSys, a reconfigurable computing system developed to investigate the effectiveness of combining reconfigurable hardware with(More)
A major obstacle in designing dynamically scheduled processors is the size and port requirement of the register file. By using a multiple banked register file and performing dynamic result renaming, a scalable register file architecture can be implemented without performance degradation. In addition, a new hybrid register renaming technique to efficiently(More)
In this paper, we present the MorphoSys reconfigurable architecture, which combines a configurable array of processing elements with a RISC processor core. We provide a system-level model, describing the array architecture and the inter-connection network. We give several examples of applications that can be mapped to the MorphoSys architecture. We also(More)
This paper introduces MorphoSys, a parallel system-on-chip which combines a RISC processor with an array of coarse-grain reconfigurable cells. MorphoSys integrates the flexibility of general-purpose systems and high performance levels typical of application-specific systems. Simulation results presented here show significant performance enhancements for(More)
This paper introduces a new interconnec tion network for massively parallel systems referred to as star connected cycles (SCC) graph. The SCC presents a fixed degree structure that results in several advantages over variable degree graphs like the star graph and the n-cube. The description of the SCC graph given in this paper in cludes issues such as(More)
Lel G be a graph with vertex connectivi2y k(G). An important measure of the fault tolerance of G is its faul&diameler df(G), which is defined as the maximum diameter resulting from the deletion of any set of nodes containing less than k(G) nodes. The robustness of G is often measured by comparing d/(G) with the diameter of Ihe fault-free G, namely d(G). In(More)
In this paper, we present a case study for the design, programming and usage of a reconfigurable system-on-chip, MorphoSys, which is targeted at computation-intensive applications. This 2-million transistor design combines a reconfigurable array of cells with a RISC processor core and a high bandwidth memory interface. The system architecture, software(More)