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- Nabeel Shirazi, Al Walters, Peter M. Athanas
- FCCM
- 1995

Many algorithms rely on floating point arithmetic for the dynamic range of representations and require millions of calculations per second. Such computationally intensive algorithms are candidates for acceleration using custom computing machines (CCMs) being tailored for the application. Unfortunately, floating point operators require excessive area (or… (More)

Automatic bitwidth analysis is a key ingredient for highlevel programming of FPGAs and high-level synthesis of VLSI circuits. The objective is to find the minimal number of bits to represent a value in order to minimize the circuit area and to improve efficiency of the respective arithmetic operations, while satisfying user-defined numerical constraints. We… (More)

Visual data flow environments are ideally suited for modeling digital signal processing (DSP) systems, as many DSP algorithms are most naturally specified by signal flow graphs. Although several academic and commercial frameworks provide a high level of abstraction for modeling DSP systems, they have drawbacks as design tools for FPGAs. They do not provide… (More)

- Wayne Luk, Nabeel Shirazi, Peter Y. K. Cheung
- FCCM
- 1997

This paper describes a framework and tools for automating the production of designs which can be partially recon gured at run time. The tools include: (i) a partial evaluator, which produces con guration les for a given design, where the number of con gurations can be minimised by a process known as compile-time sequencing; (ii) an incremental con guration… (More)

- Wayne Luk, Nabeel Shirazi, Shaori Guo, Peter Y. K. Cheung
- FPL
- 1997

Pipeline morphing is a simple but e ective technique for recon guring pipelined FPGA designs at run time. By overlapping computation and recon guration, the latency associated with emptying and re lling a pipeline can be avoided. We show how morphing can be applied to linear and mesh pipelines at both word-level and bit-level, and explain how this method… (More)

- Wayne Luk, Nabeel Shirazi, Peter Y. K. Cheung
- FCCM
- 1996

We present a simple model for specifying and optimising designs which contain elements that can be reconfigured at run-time. In this model the control mechanism for reconfiguration can be implemented in many ways: by the user using multiplexers or other logic blocks, or by FPGAs which support dynamic partial reconfiguration. The model can be used for… (More)

- Vinay Singh, Ann Root, E. Hemphill, Nabeel Shirazi, James Hwang
- FCCM
- 2003

- Nabeel Shirazi, Wayne Luk, Peter Y. K. Cheung
- FCCM
- 1998

This paper describes a method that automates a key step in producing run-time recon gurable designs: the identi cation and mapping of recongurable regions. In this method, two successive circuit con gurations are matched to locate the components common to them, so that recon guration time can be minimized. The circuit congurations are represented as a… (More)

- Nabeel Shirazi, Wayne Luk, Peter Y. K. Cheung
- FPL
- 1998

A method for managing reconngurable designs, which supports run-time connguration transformation, is proposed. This method involves structuring the reconnguration manager into three components: a monitor, a loader, and a connguration store. Diierent trade-oos can be achieved in connguration time, optimality of the conngured circuits, and the complexity of… (More)