N. Shylashree

Publications8
h-index2
Citations14
Highly Influential Citations0
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Hardware realization of fast elliptic curve point multiplication using balanced ternary representation and pre-computation over GF(p)
Abstract We present a new hardware realization of fast elliptic curve Point Multiplication (PM) using the balanced ternary representation of the scalar multiplier. This hardware implementation uses… Expand
  • 1
Efficient Implementation of Scalar Multiplication for Elliptic Curve Cryptography using Ancient Indian Vedic Mathematics over GF(p)
TLDR
This paper examines that computation can be speeded up by using Ancient Indian Vedic Mathematics to speed up the Scalar multiplication. Expand
  • 4
Three level heterogeneous clustering protocol for wireless sensor network
TLDR
The restricted battery of the sensors has always been a bottleneck for the WSNs. Expand
  • 7
Effective resistance calculation and automated solution for fixing reliability verification violations
This paper covers the automation done to upgrade the reliability verification in the backend circuit design of microchips. Automation is done to upgrade the reduction of violations which occurs… Expand
UVM-based Logic Verification of Input Output Interface
TLDR
This paper presents a block level verification of a subsystem called Input Output Interface. Expand
Efficient Implementation of RSA Encryption and Decryption using Ancient Indian Vedic Mathematics
RSA is one of the safest standard algorithms, based on public-key, for providing the security in communication and networks. One of the most time consuming processes in RSA algorithm for… Expand
  • 2
Two Stage Block Truncation Coding for Lower Mean Square Error
In basic Block Truncation Coding, the given data sequence is encoded into a two level quantized approximation. This results in two segments one of which is comprised of the high level value and the… Expand
Design of a Delta Threshold Voltage Difference based fully Embedded Read Only Memory along with a Skew Sense Amplifier
TLDR
This paper describes the design and implementation of an embedded ROM memory along with its sense amplifier. Expand