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Quantitative analysis of floating point arithmetic on FPGA based custom computing machines
TLDR
In this paper, we show how to accelerate real-time floating point arithmetic algorithms using custom CCMs by using higher-level languages, like VHDL. Expand
Compilation tools for run-time reconfigurable designs
TLDR
This paper describes a framework and tools for automating the production of designs which can be partially reconfigured at run time. Expand
Modelling and optimising run-time reconfigurable systems
TLDR
We present a simple model for specifying and optimising designs which contain elements that can be reconfigured at run-time. Expand
System Level Tools for DSP in FPGAs
TLDR
In this paper, we describe a new software tool called System Generator for modeling and designing DSP systems in a visual data flow environment. Expand
Pipeline morphing and virtual pipelines
TLDR
Pipeline morphing is a simple but effective technique for reconfiguring pipelined FPGA designs at run time. Expand
Accelerating bit error rate testing using a system level design tool
TLDR
We demonstrate how system level design tools for creating DSP designs reduce the amount of time needed to create a DSP design, in part by eliminating the need for verification between system model and hardware implementation. Expand
Floating-point bitwidth analysis via automatic differentiation
TLDR
We present a novel approach to bitwidth- or precision-analysis for floating-point designs. Expand
Run-Time Management of Dynamically Recongigurable Designs
TLDR
A method for managing reconfigurable designs, which supports run-time configuration transformation, is proposed. Expand
Automating production of run-time reconfigurable designs
TLDR
This paper describes a method that automates a key step in producing run-time reconfigurable designs: the identification and mapping of reconfigable regions. Expand
Implementation of a 2-D Fast Fourier Transform on an FPGA-Based Custom Computing Machine
TLDR
The two dimensional fast Fourier transform (2-D FFT) is an indispensable operation in many digital signal processing applications but yet is deemed computationally expensive when performed on a conventional general purpose processors. Expand
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