• Publications
  • Influence
Synthesis of Reactive(1) Designs
TLDR
It is shown that for many expressive specifications of hardware designs the problem of synthesizing digital designs from their ltl specification can be solved in time N3, where N is the size of the state space of the design.
Strategy logic
From Nondeterministic Buchi and Streett Automata to Deterministic Parity Automata
  • N. Piterman
  • Computer Science
    21st Annual IEEE Symposium on Logic in Computer…
  • 12 August 2006
TLDR
This paper shows how to construct deterministic automata with fewer states and, most importantly, parity acceptance conditions and revisits Safra's determinization constructions.
Decoding the Regulatory Network for Blood Development from Single-Cell Gene Expression Measurements
TLDR
This work describes a strategy that combines gene expression profiling of large numbers of single cells with data analysis based on diffusion maps for dimensionality reduction and network synthesis from state transition graphs to generate a computationally executable transcriptional regulatory network model of blood development.
From Nondeterministic Büchi and Streett Automata to Deterministic Parity Automata
  • N. Piterman
  • Computer Science
    Log. Methods Comput. Sci.
  • 16 May 2007
TLDR
This paper shows how to construct deterministic automata with fewer states and parity acceptance conditions, and revisits Safra's determinization constructions for automata on infinite words.
Enhanced Vacuity Detection in Linear Temporal Logic
TLDR
This work investigates vacuity detection with respect to subformulas with multiple occurrences with growing awareness of the importance of suspecting the system or the specification of containing an error in cases where model checking succeeds.
Generalized Parity Games
TLDR
This work considers games where the winning conditions are disjunctions (or dually, conjunctions) of parity conditions; it shows that these games retain the computational complexity of Rabin and Streett conditions, and proves (co-)NP-hardness for the special case of a conjunction/disjunction of two parity conditions.
Specify, Compile, Run: Hardware from PSL
From liveness to promptness
TLDR
Various problems related to PROMPT-LTL, including realizability, model checking, and assume-guarantee modelchecking, are studied and shown that they can be solved by techniques that are quite close to the standard techniques for LTL.
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