N. V. Satyanarayana

We don’t have enough information about this author to calculate their statistics. If you think this is an error let us know.
Learn More
In this paper, we propose an architecture for controlling Dynamic Reconfigurable systems. The processor instructions when compiled one by one produces very high delay overhead. If these instructions are converted into a combinational logic then the overhead can be reduced thereby making the system an efficient one. This paper presents a method for creating(More)
  • 1