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This paper presents designs and measurements of distributed amplifiers (DAs) processed on a 130-nm silicon-on-insulator CMOS technology on either standard-resistivity (10 Omegamiddotcm) or high-resistivity (>1 kOmegamiddotcm) substrates, and with either body-contacted (BC) or floating-body (FB) MOSFETs. Investigations have been carried out to assess the(More)
The behavior of an integrated traveling wave amplifier (TWA), fabricated in a 130 nm silicon-on-insulator (SOI) CMOS process, has been characterized over a temperature range from 25/spl deg/C to 250/spl deg/C. The TWA is a four-stage cascode design which uses floating body (FB) transistors and microstrip lines as passives. A gain of 7 dB with a 0.4-27 GHz(More)
In this paper, the design and measurement results of a CMOS partially depleted silicon-on-insulator (SOI) traveling-wave amplifier (TWA) are presented. The four-stage TWA is designed with a single common source nMOSFET in each stage using a 130-nm SOI CMOS technology requiring a chip area of 0.75 mm<sup>2</sup>. A gain of 4.5 dB and a unity-gain bandwidth(More)
The design of a single shot sampling circuit allowing 20GHz bandwidth random signal and the experimental results of the main circuits are described. Assuming a temporal analysis depth of 5ns, this circuit, based on the principle of non simultaneous spatial sampling and realized in InP HBT MMIC (FT=180GHz) and CPW propagation line, can reach a truly sampling(More)
Targeting [DC-20 GHz] bandwidth and 40 GS/s sampling rate for high dynamic range (60 dB) ultra fast signal analysis, we present the preliminary experimental results obtained on InP-InGaAs-InP double heterojunction bipolar transistor based MMIC (FT = 180 GHz). The critical circuits leading to wide band signal sampling operation are made of high bandwidth(More)
In this paper, the design and the results of two CMOS silicon-on-insulator (SOI) distributed amplifiers (DA) are presented. Partially-depleted SOI process using microstrip lines, and floating-body (FB) transistors are considered. The measured gain is around 4.5 dB with a 0.4-30 GHz bandwidth for the common source DA (CSDA) and around 7 dB with a 0.4-26 GHz(More)
This paper describes the design and realization of a buffered track and hoId (BTH) circuit fabricated in InP-InGaAs-InP double heterojunction bipolar transistor (DHBT) technology (F<sub>T</sub> = 180 GHz). This BTH is intended for a single shot, 20 GHz bandwidth and 40 GS/s sampling frequency digitizer based on the non simultaneous spatial sampling(More)
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