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In this paper, we present a methodology for mapping an Embedded Signal Processing ESP application onto HPC platforms such that the throughput performance is maximized. Previous approaches used a linear pipelined execution model which restrict the mapping choices. We show that the optimal" solution obtained under that model can be improved, using the(More)
The architecture of the latest Graphic Processing Unit (GPU) has surpassed the previous application-specific stream architecture. They consist of a number of uniform programmable units integrated on the same chip which facilitate the general-purpose computing beyond the graphic processing. With the multiple programmable units executing in parallel, the(More)
Traditionally, an implementation of mixed reality systems requires tight and accurate spatial/visual registration between the real and virtual objects. Any meaningful interaction is only possible within this "tightly" coupled mixed reality world. Thus, the degree of this spatial and explicit registration has been regarded one of the most important factors(More)
Chip Multi-Processor (CMP) has recently become a mainstream microprocessor. CMP's allow multiple threads executing on a single processor chip at the same time, thus promise to deliver higher throughput performance. However, resource sharing among the threads executing on the same processor chip can cause conflicts and hurt the performance. Thus obtaining(More)