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Space Time Adaptive Processing (STAP) techniques that are being developed for the next generation radar systems require very high computing power. In order to meet the real-time requirements in STAP applications, High Performance Computing (HPC) systems are used. In this paper, we present a methodology to design high throughput-rate parallel algorithms for(More)
In this paper, we present a methodology for mapping an Embedded Signal Processing ESP application onto HPC platforms such that the throughput performance is maximized. Previous approaches used a linear pipelined execution model which restrict the mapping choices. We show that the optimal" solution obtained under that model can be improved, using the(More)
Traditionally, an implementation of mixed reality systems requires tight and accurate spatial/visual registration between the real and virtual objects. Any meaningful interaction is only possible within this "tightly" coupled mixed reality world. Thus, the degree of this spatial and explicit registration has been regarded one of the most important factors(More)
Chip Multi-Processor (CMP) has recently become a mainstream microprocessor. CMP's allow multiple threads executing on a single processor chip at the same time, thus promise to deliver higher throughput performance. However, resource sharing among the threads executing on the same processor chip can cause conflicts and hurt the performance. Thus obtaining(More)