Learn More
This paper presents a high speed, non-pipelined FPGA implementation of the Rijndael algorithm (Daemen, 1999), which has been selected as the new AES algorithm by the National Institute of Standards and Technology (NIST). In this study, we have implemented both the encryption and the decryption algorithms of Rijndael on the same FPGA. All the key and data(More)
A delay-insensitivity verification method is proposed for bit-level pipelined systolic dual-rail threshold logic adders, which achieve speed-up through early and input-incomplete carry output generation and which employ bit-wise completion at pipeline registers. The proposed method simplifies the verification task significantly, regardless of the operand(More)