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This paper shows four different methods to evaluate multiple-output logic functions using decision diagrams: SBDD, MTBDD, BDD for characteristic functions (CF), and BDDs for ECFNs (Encoded Characteristic Function for Non-zero outputs). Methods to compute average evaluation time for each type of decision diagrams are presented. By experimental analysis using… (More)

This paper shows a method to decompose a given multiple-output circuit into two circuits with intermediate outputs. We use a BDD for characteristic function (BDD for CF) to represent a multiple-output function.Many benchmark functions were realized by LUT cascades with intermediate outputs. Especially, adders and a binary to BCD converter were successfully… (More)

—The traditional problem in binary decision diagrams (BDDs) has been to minimize the number of nodes since this reduces the memory needed to store the BDD. Recently, a new problem has emerged: minimizing the average path length (APL). APL is a measure of the time needed to evaluate the function by applying a sequence of variable values. It is of special… (More)

This paper shows four different methods to evaluate multiple-output logic functions using decision diagrams: Shared BDD (SBDD), Multi-Terminal BDD (MTBDD), BDD for characteristic functions (CF), and BDDs for Encoded Characteristic Function for Non-zero outputs (ECFNs). Methods to compute average evaluation time for each type of decision diagrams are… (More)

—This paper shows an implementation of CAN-SCID (Combined Architecture for Stream Categorization and Intrusion Detection). To satisfy the required system throughput, the packet assembler and the regular expression matching are implemented by the dedicated hardware. On the other hand, the counting of matching results and the system control are implemented by… (More)

A sequential realization of multiple-output logic functions is presented. A c onventional sequential realization is based on SBDDs (Shared r educed o r dered Binary Decision Diagrams). In this paper, we propose PQMDD (Paged Quasi-reduced o r dered Multi-valued Decision Diagram) as a new data structure. A function is represented by a PQMDD, and stored in… (More)

In this paper, we propose a regular expression matching circuit based on a decomposed automaton. To implement a regular expression matching circuit , first, we convert regular expressions into a non-deterministic finite automaton (NFA). Then, to reduce the number of states, we convert the NFA into a modular non-deterministic finite automaton with unbounded… (More)

An address generator produces a unique address from 1 to k for the input that matches to one of k registered vectors, and produces 0 for other inputs. This paper presents the super hybrid method to design an address generator. The hash memories realize about 96% of the registered vectors, while the reconfigurable PLA realizes the remaining 4% of the… (More)

This paper shows a design method for a sequential circuit by using a Look-Up Table (LUT) ring. An LUT ring consists of memories , a programmable interconnection network, a feedback register , an output register, and a control circuit. It sequentially emulates an LUT cascade that represents the state transition functions and the output functions. We present… (More)

SUMMARY This paper represents a cycle-based logic simulation method using an LUT cascade emulator, where an LUT cascade consists of multiple-output LUTs (cells) connected in series. The LUT cascade emulator is an architecture that emulates LUT cascades. It has a control part, a memory for logic, and registers. It connects the memory to registers through a… (More)