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A realization of multiple-output logic functions using a RAM and a sequencer is presented. First, a multiple-output function is represented by an encoded characteristic function for non-zeros (ECFN). Then, it is represented by a cascade of look-up tables (LUTs). And finally, the cascade is simulated by a RAM and a sequencer. Multiple-output functions for(More)
This paper shows four different methods to evaluate multiple-output logic functions using decision diagrams: SBDD, MTBDD, BDD for characteristic functions (CF), and BDDs for ECFNs (Encoded Characteristic Function for Non-zero outputs). Methods to compute average evaluation time for each type of decision diagrams are presented. By experimental analysis using(More)
A multiple-output function can be represented by a binary decision diagram for characteristic function (BDD for CF). This paper presents a new method to represent multiple-output incompletely specified functions using BDD for CF. An algorithm to reduce the widths of BDD for CFs is presented. This method is useful for decomposition of incompletely specified(More)
This paper shows a new method to represent a multiple-output function: an encoded characteristic function for non-zero outputs (ECFN).. The binary decision diagrams (BDDs) for ECFNs are never greater than corresponding SBDDs. The size of a BDD depends on the encoding of the outputs as well as the ordering of the variables. We conjecture that there exists an(More)
Pseudo-Kronecker decision diagram (PKDD) is a generalization of binary decision diagram (BDD). A PKDD requires not more nodes than a BDD to represent the same function. In this paper, we consider a method to represent incompletely specified functions by using PKDDs. We developed a heuristic method to obtain PKDDs. Many PKDDs for MCNC benchmark functions(More)
This paper shows a method to decompose a given multiple-output circuit into two circuits with intermediate outputs. We use a BDD for characteristic function (BDD for CF) to represent a multiple-output function.Many benchmark functions were realized by LUT cascades with intermediate outputs. Especially, adders and a binary to BCD converter were successfully(More)
—The traditional problem in binary decision diagrams (BDDs) has been to minimize the number of nodes since this reduces the memory needed to store the BDD. Recently, a new problem has emerged: minimizing the average path length (APL). APL is a measure of the time needed to evaluate the function by applying a sequence of variable values. It is of special(More)
{ A hardware logic simulation engine based on decision diagrams is presented. For the data structure of the engine, we propose PMDDs (Paged reduced ordered Multi-valued Decision Diagrams). A unit of this engine consists of memory (RAMs) and control circuits: RAMs store the PMDD data, and the control circuits trace the edges according to the input vectors.(More)
This paper shows four different methods to evaluate multiple-output logic functions using decision diagrams: Shared BDD (SBDD), Multi-Terminal BDD (MTBDD), BDD for characteristic functions (CF), and BDDs for Encoded Characteristic Function for Non-zero outputs (ECFNs). Methods to compute average evaluation time for each type of decision diagrams are(More)
—This paper shows an implementation of CAN-SCID (Combined Architecture for Stream Categorization and Intrusion Detection). To satisfy the required system throughput, the packet assembler and the regular expression matching are implemented by the dedicated hardware. On the other hand, the counting of matching results and the system control are implemented by(More)