Mun-Yang Park

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This study presents a 1–5.6 Gb/s CMOS clock and data recovery (CDR) integrated circuit (IC) implemented in a 0.13 μm CMOS process. The CDR uses a half-rate linear phase detector (PD) of which static phase offset is compensated by an additional binary PD and a digital charge pump (CP) calibration block. During initialisation, the static phase offset is(More)
A fully differential dual input CMOS transconductor, with high linearity and low distortion, is proposed. To achieve high performance characteristics at low supply voltage, three design considerations are described from the viewpoint of DC-offsets, linear range, and distortions. A 1.8 V 10 MHz fully-differential 3/sup rd/-order Chebyshev Gm-C low pass(More)
This paper presents the design of a low-power smallsize transmitter with discrete-time baseband filter for LTE application operating at 1.8-2 GHz. The transmitter achieves 4.5 dBm output power with more than -46 dBc of LO feedthrough suppression and -38 dBc image rejection ratio. At -0.3 dBm transmitted power of LTE 5 MHz channel, ACLR is measured below -42(More)
A fully integrated receiver front-end, reconfigured by a frequency locking scheme using a PLL, is implemented in a 0.18 /spl mu/m triple-well CMOS technology. The receiver front-end is composed of a discretely tunable low noise amplifier (DT-LNA), a quadrature down mixer, and a discretely and continuously tunable frequency synthesizer (DCT-FS) with an(More)
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