Muhammed S. Khairy

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Recent power reduction techniques aggressively modulate the supply voltage of embedded buffering memories allowing acceptable hardware errors to flow through the processing chain. In this paper, we present a model that captures the statistics of both channel noise and hardware failures. We further introduce a modified Viterbi decoder that maximizes the(More)
This paper presents a single, scalable, unified statistical model that accurately reflects the impact of random embedded memory failures due to power management policies on the overall performance of a communication system. The proposed framework enables system designers to efficiently and accurately determine the effectiveness of novel power management(More)
As a result of supply voltage reduction and process variations effects, the error free margin for dynamic voltage scaling has been drastically reduced. This paper presents an error aware model for arithmetic and logic circuits that accurately and rapidly estimates the propagation delays of the output bits in a digital block operating under voltage scaling(More)
In current broadband MIMO-OFDM systems such as 3GPP LTE, embedded buffering memories occupy a large portion of chip area and a significant amount of power consumption. Due to the dense structure of memories, they are especially vulnerable to scaling effects such as process variation. These effects (hardware errors) become more pronounced when aggressive(More)
In the widely used OFDM (Orthogonal Frequency Division Multiplexing) systems, the FFT and IFFT pair are integral parts used to modulate and demodulate the data constellation on the sub-carriers. Within such systems, embedded buffering memories occupy a large portion of the area and hence directly control the overall metrics of the system including power(More)
In a broadband MIMO-OFDM wireless communication system, embedded buffering memories occupy a large portion of the chip area and a significant amount of power consumption. Due to process variations of advanced CMOS technologies, it becomes both challenging and costly to maintain perfectly functioning memories under all anticipated operating conditions. Thus,(More)
This paper exploits the predominance of embedded memories in current and emerging wireless transceivers as a means to save power via channel state aware voltage scaling. The paper presents a statistical model that captures errors in embedded memories due to voltage over-scaling and maps the errors to a Gaussian distribution that represents a combination of(More)
Due to supply voltage reduction and process variations effects, the error free margin for dynamic voltage scaling has been drastically reduced. Thus, supply-Voltage Over Scaling (VOS) has emerged as an efficient means to achieve ultra-low energy efficient systems, that tradeoff energy efficiency and reliability. Recently, N-Modular Redundancy (NRM) has been(More)
Mobile wireless systems are typically designed assuming worst-case propagation scenarios, a situation that occurs infrequently in real-life. To reduce power, we exploit the dynamic and statistical nature of wireless signals to aggressively scale the supply voltage using Voltage over Scaling (VoS) on buffering memory modules during run-time. VoS introduces a(More)
This paper presents a novel statistical state-dependent timing model for voltage over scaled (VoS) logic circuits that accurately and rapidly finds the timing distribution of output bits. Using this model erroneous VoS circuits can be represented as error-free circuits combined with an error-injector. A case study of a two point DFT unit employing the(More)