Muhammad S. Khairy

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Graphic Processing Units (GPUs) have evolved to provide a massive computational power. In contrast to Central Processing Units, GPUs are so-called many-core processors with hundreds of cores capable of running thousands of threads in parallel. This parallel processing power can accelerate the simulation of communication systems. In this work, we utilize(More)
To guard against process variability in advanced semiconductor nodes, especially for high-density memories, designers resort to overdesigning policies resulting in increased power consumption. A promising approach to save power is to utilize Voltage over-Scaling (VoS). However VoS results into unreliable buffering memories where a predictable statistically(More)
This paper presents a reduced-complexity low power error-resilient K-Best MIMO Detector. A novel tree-enumeration method is proposed such that the error-resilient detection processes a reduced search space and is more suitable for VLSI design. Moreover, a circuit-level optimization is employed to further simplify the complexity. Experimental results are(More)
As fault rates increase when technology advances from one node to another, fault tolerance becomes vital for the reliability of arithmetic circuits. This work represents an attempt to achieve fault tolerance for a combined IEEE decimal-64/binary-64 floating point redundant adder by using residue codes. To our knowledge, this is the first implementation of a(More)
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