Muhammad Raashid Khan

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The proposed low noise amplifier was implemented in IBM 0.13um CMOS technology. Powered by a 1.2 V supply and the simulated DC current consumption is only 10.9mA. In Figure 7, S11 is below -10dB ranging from 300MHz to 3.3GHZ, with a bandwidth of around 3GHz. S21indicates the gain of the LNA. As shown, the gain of higher than 10dB is over the frequency(More)
In this paper, an input inductive network for the wideband LNA is proposed. The two input inductors located in and out of the feedback loop are set respectively to combine with the conventional resistive feedback structure. Input matching and NF of the LNA can be optimized separately by varying the value of the two input inductors without significant(More)
The step monopole is presented for the frequency range from 5.5 GHz to 13.73 GHz (more than 84%) and with a maximum gain of 6.07 dBi. The increased radius enhanced the bandwidth, and the small ground plane 6cm×6cm enhanced the impedance matching. An omni-directional radiation pattern is achieved in XY-plane of the antenna. This antenna could be used(More)
This paper presents a low power, high linearity wideband cascode low noise amplifier (LNA) targeting the GSM/LTE standards and RFID reader applications. The common source (CS) stage is considered to be the dominated nonlinearity source for cascode LNA and the modified derivative superposition (MDS) technology is adopted to improve the linearity of this(More)
A small integrated antenna was designed for the inter-chip and intra-chip communication over the frequency band from 13.5GHz to 18.3GHz. The FR4 substrate is used to improve the gain of the antenna. The gain of the antenna varies between -5.14dB to -2.3dB which is reasonable gain for the inter- and intra-chip communication.
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