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Negative bias temperature instability has become an important reliability concern for ultra-scaled Silicon IC technology with significant implications for both analog and digital circuit design. In this paper, we construct a comprehensive model for NBTI phenomena within the framework of the standard reaction–diffusion model. We demonstrate how to solve the(More)
One of the major reliability concerns in nanoscale very large-scale integration design is the time-dependent negative- bias-temperature-instability (NBTI) degradation. Due to the higher operating temperature and increasing vertical oxide field, threshold voltage (V<sub>t</sub>) of PMOS transistors can increase with time under NBTI. In this paper, we examine(More)
On-the-fly and Ultra-fast V T are popular characterization techniques for analyzing NBTI degradation. We show that these techniques do not probe the intrinsic NBTI degradation directly and hence require suitable correction. The 'corrected' data allows us to explore the subtlety of relaxation dynamics by various measurements and suggest a theoretical basis(More)
An Ultra-Fast On-The-Fly (UF-OTF) I DLIN technique having 1µs resolution is developed and used to study gate insulator process dependence of NBTI in Silicon Oxynitride (SiON) p-MOSFETs. The Nitrogen density at the Si-SiON interface and the thickness of SiON layer are shown to impact temperature, time, and field dependencies of NBTI. The plausible material(More)
Negative bias temperature instability (NBTI) is a well-known reliability concern for PMOS transistors. We review the literature to find seven key experimental features of NBTI degradation. These features appear mutually inconsistent and have often defied easy interpretation. By reformulating the Reaction–Diffusion model in a particularly simple form, we(More)
Negative Bias Temperature Instability (NBTI) is studied in p-MOSFETs having Decoupled Plasma Nitrided (DPN) gate oxides (EOT range of 12A O through 22A O). Threshold voltage shift (∆V T) is shown to be primarily due to interface trap generation (∆N IT) and significant hole trapping (∆N OT) has not been observed. ∆V T follows power-law time (t) dependence(More)
– Reaction-Diffusion (R-D) framework for interface trap generation along with hole trapping in pre-existing and generated bulk oxide traps are used to model Negative Bias Temperature Instability (NBTI) in differently processed SiON p-MOSFETs. Time, temperature and bias dependent degradation and recovery transients are predicted. Long-time power law exponent(More)
Negative bias temperature instability (NBTI) has become one of the major causes for temporal reliability degradation of nanoscale circuits. In this paper, we analyze the temporal delay degradation of logic circuits due to NBTI. We show that knowing the threshold voltage degradation of a single transistor due to NBTI, one can predict the performance(More)
—Recent advances in experimental techniques (on-the-fly and ultrafast techniques) allow measurement of threshold voltage degradation due to negative-bias temperature instability (NBTI) over many decades in timescale. Such measurements over wider temperature range (−25 • C to 145 • C), film thicknesses (1.2–2.2 nm of effective oxide thickness), and(More)
Negative bias temperature instability (NBTI) in MOSFETs is one of the major reliability concerns in sub-100nm technologies. So far, studies of NBTI and its impact on circuit performance have assumed an average behavior of the degradation process. However, in very short channel devices, finite number of <i>Si-H</i> bonds in the channel can induce a(More)