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Large last-level caches (L 3 Cs) are frequently used to bridge the performance and power gap between processor and memory. Although traditional processors implement caches as SRAMs, technologies such as STT-RAM (MRAM), and eDRAM have been used and/or considered for the implementation of L 3 Cs. Each of these technologies has inherent weaknesses: SRAM is(More)
—Ever-growing application data footprints demand faster main memory with larger capacity. DRAM has been the technology choice for main memory due to its low latency and high density. However, DRAM cells must be refreshed periodically to preserve their content. Refresh operations negatively affect performance and power. Traditionally, the performance and(More)
Gain cell memories feature high speed, low power, and high density, which are suitable for SoC designs. In this paper, low power techniques to reduce leakage currents for 2T1D gain cell memory array are presented. For each memory cell, p-type gated diode storage device is applied. In addition, footer power gating and foot driver are applied on each memory(More)
Large last-level caches (L<sup>3</sup>Cs) are frequently used to bridge the performance and power gap between processor and memory. Although traditional processors implement caches as SRAMs, technologies such as STT-RAM (MRAM), and eDRAM have been used and/or considered for the implementation of L<sup>3</sup>Cs. Each of these technologies has inherent(More)
First-in first-out (FIFO) memories are widely used in SoC for data buffering and flow control. In this paper, a robust ultra-low power asynchronous FIFO memory is proposed. With self-adaptive power control and complementary power gating techniques, leakage power of the FIFO memory array is minimized. Moreover, with the proposed dual-V T 7T SRAM cell, the(More)
Memory systems are critical to system responsivenessand operating costs. New memory technologies like PCM, STT-MRAM, RRAM are poised to provide an intermediatememory layer between DRAM and flash to better serve the needs of capacity, latency hungry datacenter applications. To drive their efficient deployment, it is imperative to make complex architectural(More)
Large last-level cache (L 3 C) is efficient for bridging the performance and power gap between processor and memory. Several memory technologies, including SRAM, STT-RAM (MRAM), and embedded DRAM (eDRAM), have been used or considered as the technology to implement L 3 Cs. However, each of them has inherent weaknesses: SRAM is relatively low density and(More)
This paper presents a cached DIMM architecture - a low-latency and energy-efficient memory system. Two techniques are proposed: the on-DIMM cache and the on-DIMM cache-aware address mapping scheme. These two techniques work together to reduce the memory access latency. Based on the benchmarks considered, our experiments show that compared to a conventional(More)
Isr develops, applies and teaches advanced methodologies of design and analysis to solve complex, hierarchical, heterogeneous and dynamic problems of engineering technology and systems for industry and government. Isr is a permanent institute of the university of maryland, within the a. James clark school of engineering. It is a graduated national science(More)