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  • Jiajun Shi, Deepak Nayak, Motoi Ichihashi, Srinivasa Banna, Csaba Andras Moritz
  • Engineering, Computer Science
  • IEEE Computer Society Annual Symposium on VLSI…
  • 2016 (First Publication: 11 July 2016)
  • Conventional 2D CMOS faces severe challenges sub-22nm nodes. The monolithic 3D (M3D) IC technology enables ultra-high density vertical connections and provides a good path for technology nodeContinue Reading
  • Sandeep Kumar Samal, Deepak Nayak, Motoi Ichihashi, Srinivasa Banna, Sung Kyu Lim
  • Computer Science
  • IEEE/ACM International Conference on Computer…
  • 2016 (First Publication: 7 November 2016)
  • In this paper, we develop tier partitioning strategy to mitigate back-end-of-line (BEOL) interconnect delay degradation and cost issues in monolithic 3D ICs (M3D). First, we study the routingContinue Reading
  • Koichiro Ishibashi, Tetsuya Fujimoto, +11 authors Toshiro Tsukada
  • Engineering, Computer Science
  • IEICE Trans. Electron.
  • 2006 (First Publication: 1 March 2006)
  • Circuit techniques for realizing low-voltage and low-power SoCs for 90-nm CMOS technology and beyond are described. A proposed SAFBB (self-adjusted forward body bias techniques), ATC (AsymmetricContinue Reading
  • Motoi Ichihashi, Jia Zeng, +4 authors Jongwook Kye
  • Engineering, Computer Science
  • 29th IEEE International System-on-Chip Conference…
  • 2016 (First Publication: 1 September 2016)
  • This paper discusses the performance impact of interconnect parasitic resistance and capacitance for SoC (System on Chip) design beyond 10-nm FinFET technology. As technology scaling advances, theContinue Reading
  • Youngtag Woo, Motoi Ichihashi, S. R. Parihar, Lei Yuan, Srinivasa Banna, Jongwook Kye
  • Physics
  • IEEE International Electron Devices Meeting (IEDM…
  • 2015 (First Publication: 1 December 2015)
  • Due to the resolution limit of the lithography tools, multiple patterning technologies are being introduced to the back-end of the line (BEOL). For example, LELELE (or LE3, triple litho-etch) or SADPContinue Reading
  • Motoi Ichihashi, Youngtag Wood, Muhammed Ahosan Ul Karim, Vivek Joshi, David Burnett
  • Materials Science, Computer Science
  • 31st IEEE International System-on-Chip Conference…
  • 2018 (First Publication: 1 September 2018)
  • This paper describes a high-speed memory design with a 10-transistor (10T) differential-signal SRAM cell in a 14-nm FinFET technology. The 10T SRAM cell is 2.63 times larger than the smallest 6 $T$Continue Reading
  • Motoi Ichihashi, Hélène Lhermet, Edith Beigné, Frédéric Rothan, Marc Belleville, Amara Amara
  • Computer Science
  • PATMOS
  • 2009 (First Publication: 9 September 2009)
  • In this paper, we propose an on-chip dc-dc buck converter for fine-grain dynamic voltage scaling (DVS) on a multi-power domain SoC. The proposed circuit converts from the I/O voltage to the requiredContinue Reading