Motohiro Nakagawa

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We developed an image processing platform RASH-IP on the basis of development know-how of FPGA-based parallel machine RASH. RASH-IP contains six ALTERA Stratix (EP1S25) FPGAs on the VME board. RASH-IP boards have 10 buses in order to transfer HDTV video image data with several FPGAs. Each FPGA is directly connected to an 8M-byte synchronous SRAM so that it(More)
An on-chip analysis technique for SOC, which enables system performance to be improved, was developed. The key to this technique is the synchronized analysis of the whole SOC. This is made possible by a circuit structure in which small circuits for analysis are distributed at points on the SOC to be analyzed, and these circuits operate in synchronization(More)
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