Morteza S. Alavi

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We propose a novel digital I/Q modulator implemented in 65 nm CMOS technology. Using in-phase (I) and quadrature-phase (Q) clock signals with a 25% duty cycle, the modulator can directly construct the RF output signal using four transistor switch banks with a power combiner. The circuit achieves 12.6 dBm peak output power and 20% peak drain efficiency at 2(More)
This paper presents a 2×13-bit I/Q RF-DAC-based all-digital modulator realized in 65 nm CMOS. The proposed quadrature up-converter uses a 25% duty-cycle clock to isolate the in-phase (I) and quadrature-phase (Q) modulating signals before combining. Using a 1.2 V supply and an on-chip power combiner, the modulator provides more than 21 dBm RF output(More)
In this paper, we present a fully integrated RFDAC-based outphasing power amplifier (ROPA) in 40-nm CMOS that achieves 22.2 dBm peak output power with 49.2% drain efficiency at 5.9 GHz. It employs differential quasi-load-insensitive Class-E branch PAs that can dynamically be segmented using a 3-bit digital amplitude control word to improve efficiency at(More)
To fully benefit from the progress of CMOS technologies, it is desirable to completely digitize the TX, replacing its final stage with a digitally controlled PA (DPA). The DPA consists of arrays of small sub-PAs that are digitally controlled to modulate the output amplitude, thus operating as an RF-DAC [1–6]. DPAs are normally designed in a switched(More)
This paper presents an intrinsically linear wideband polar digital power amplifier (DPA) operating in semi class-E/F<sub>2</sub> mode. Without using any type of digital pre-distortion (DPD), the proposed architecture achieves high linearity by accurately controlling its AM&#x2013;AM and AM&#x2013;PM characteristic curves through <italic>nonlinear(More)
This paper presents an advanced 2.3&#x2013;2.8 GHz fully-integrated digital-intensive polar Doherty transmitter realized in 40nm standard CMOS. The proposed architecture comprises CORDIC, digital delay aligners, interpolators, digital pre-distortion (DPD) circuitry in combination with frequency-agile wideband phase modulators followed by the digital main(More)
This paper presents a wideband 2 &#x00D7;13-bit in-phase/quadrature-phase (I/Q) RF digital-to-analog converter-based all-digital modulator realized in 65-nm CMOS. The isolation between I and Q paths is guaranteed employing 25% duty-cycle differential quadrature clocks. With a 1.3-V supply and an on-chip power combiner, the digital I/Q transmitter provides(More)
This paper elaborates on the recently introduced concept of an all-digital RF I/Q modulator. Orthogonal summation and design procedure of the power combining network are explained in more detail. A 65 nm CMOS prototype is implemented based on this concept. The prototype achieves 12.6 dBm peak output power and 20% peak drain efficiency at 2 GHz. While(More)
This paper presents a wideband linear direct digital RF modulator (DDRM) in 40nm CMOS technology. It features an advanced 2<sup>nd</sup>-order-hold interpolation filter and I/Q-interleaving harmonic rejection RF DACs. The 2&#x00D7;9-bit DDRM core occupies 0.21mm<sup>2</sup> and consumes only 110mW at 1 GHz. Within the 0.9&#x2013;3.1GHz frequency range, the(More)
We propose a digital I/Q transmitter architecture that avoids area, complexity, noise, distortion and linearity issues of the existing solutions by allocating separate time slots to the I and Q operations during which the respective digitally-controlled RF-switched resistors, realized as arrays of MOS switches, are active. This way, the operational(More)