Morteza Damavandpeyma

Learn More
Synchronous dataflow graphs (SDFGs) are used extensively to model streaming applications. An SDFG can be extended with scheduling decisions, allowing SDFG analysis to obtain properties like throughput or buffer sizes for the scheduled graphs. Analysis times depend strongly on the size of the SDFG. SDFGs can be statically scheduled using static-order(More)
Scratchpad memories (SPMs) have become a promising on-chip storage solution for embedded systems from an energy, performance and predictability perspective. The thermal behavior of these types of memories has not been considered in detail. This thermal behavior plays an important role in the reliability of silicon devices and in their static (leakage) power(More)
Scenario-aware dataflow graphs (SADFs) efficiently model dynamic applications. The throughput of an application is an important metric to determine the performance of the system. For example, the number of frames per second output by a video decoder should always stay above a threshold that determines the quality of the system. During design-space(More)
Dynamic behavior of streaming applications can be effectively modeled by scenario-aware dataflow graphs (SADFs). Many streaming applications must provide timing guarantees (e.g., throughput) to assure their quality-of-service. For instance, a video decoder which is running on a mobile device is expected to deliver a video stream with a specific frame rate.(More)
Synchronous dataflow graphs (SDFGs) are used extensively to model streaming applications. An SDFG can be extended with scheduling decisions, allowing SDFG analysis to obtain properties, such as throughput or buffer sizes for the scheduled graphs. Analysis times depend strongly on the size of the SDFG. SDFGs can be statically scheduled using static-order(More)
The ever increasing performance gap between processors and memories is one of the biggest performance bottlenecks for computer systems. In this paper, we propose a task scheduling technique that schedules an application, modeled with a task graph, on a multiprocessor system-on chip (MPSoC) that contains a limited on-chip memory. The proposed scheduling(More)
Asynchronous digital design approach liberates VLSI systems from clock signal and offers potential for low power and high performance design methods. Due to lack of commercial CAD tools, asynchronous circuit design has not been regarded with favor. To alleviate the situation, a SystemC library is developed as an extension to the existing SystemC language to(More)
The lack of commercial CAD tools and design methodology has hindered the wide use of asynchronous designs. A high level language capable of synthesizing asynchronous circuits in a transparent manner could attract engineers to benefit from asynchronous design advantages. In this paper, a SystemC library is developed as an extension to the existing SystemC(More)
Partially depleted silicon-on-insulator (PD-SOI) technology is an appropriate fabrication process for high-performance/lowpower VLSI designs. SOI provides circuits with smaller delay and dynamic power consumption. However performance enhances come along with increase in complexity of performance measurement and delay testing. Whereas the SOI transistors are(More)
  • 1