Moo-Yeol Choi

Learn More
A 3rd-order hybrid (continuous-time and discrete-time) delta-sigma audio ADC, implemented in 65 nm CMOS process, dissipates 15 mW and occupies an active die area of 0.28 mm<sup>2</sup>. A post integration time control (PITC) technique is proposed for calibration of the RC time constant variation of the continuous-time integrator. In addition, a jitter(More)
A 2.7V 4mW per-channel 20-bit 48kS/s sigma-delta stereo audio DAC, integrated in a 0.13mum CMOS technology, achieves a dynamic range (DR) of 101dB and occupies an active die area of 0.82mm<sup>2</sup>. The transformed quantization technique is proposed to decrease tonal behavior generated in low order sigma-delta modulator and the circuit is implemented to(More)
  • 1