A new dynamic vector approach for the selection and management of the configuration of a reconfigurable superscalar processor is proposed. This new method improves on previous work that used steering vectors to guide the selection of functional units to be loaded into the processor. Dependencies among instructions in the instruction buffer are analyzed to… (More)
An architecture for a reconfigurable superscalar processor is described in which some of its execution units are implemented in reconfigurable hardware. The overall configuration of the processor is defined according to how its reconfigurable execution units are configured. An efficient micro-architectural solution to configuration management is presented… (More)
Heterogeneous multicore processors (HMPs) offer promise for significant efficiency improvement. Power-effcient cores can be paired with higher performance cores in an HMP to achieve a beneficial design in terms of both power and performance. However, such processors produce challenges in the effective mapping of threads to cores. An application could have… (More)
— In an effort to monitor and alleviate roadway traffic conditions, the Oklahoma Department of Transportation (ODOT) has deployed a statewide Intelligent Transportation Systems (ITS) architecture consisting of a large number of devices, including cameras, dynamic message signs, and speed sensors along Oklahoma highways. These devices are connected… (More)
A design process is presented for the selection of a set of instruction set extensions for the PowerPC 405 processor that is embedded into the Xilinx Virtex Family of FPGAs. The instruction set of the PowerPC 405 is extended by selecting additional instructions from the full 32-bit PowerPC instruction set architecture (ISA), of which the PowerPC 405 ISA is… (More)
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An architectural framework is studied that can perform dynamic reconfiguration. A basic objective is to dynamically reconfigure the architecture so that its configuration is well matched with the current computational requirements. The reconfigurable resources of the architecture are partitioned into N slots. The configuration bits for each slot are… (More)
CHIMAERA: A high-performance architecture with a tightly-coupled reconfigurable functional unit. A design space evaluation of grid processor architectures.