Monte P. Tull

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Practically all major metropolitan and large scale modern intelligent transportation systems have a centralized traffic management center (TMC) at their logical and functional core. The TMC provides control, coordinates system wide communications, and typically serves as a common hub from which multiple agencies plan and execute coordinated incident(More)
Single-ISA heterogeneous (also known as asymmetric) multicore processors offer significant advantages over homogenous multicores in terms of both power and performance. Power-efficient cores can be paired with higher-performance cores to achieve advantageous power/performance tradeoffs. Unfortunately, such processors also create unique challenges in(More)
An architecture for a reconfigurable superscalar processor is described in which some of its execution units are implemented in reconfigurable hardware. The overall configuration of the processor is defined according to how its reconfigurable execution units are configured. An efficient micro-architectural solution to configuration management is presented(More)
b n-1 b n-2 b 0 a0 į-n-1 į + n-2 į-0 a 0 a n-2 ..... į + 0 į + n-2 į-n-1 a n-1 1 1 1 a0 į-n-2 0 į-0 a 0 a n-2 Abstract This paper describes a new high-performance divider for binary fixed-point numbers. The divider is based on the Goldschmidt iterative algorithm and uses redundant binary number encoding of the dividend and divisor to provide improved(More)
Heterogeneous multicore processors (HMPs) offer promise for significant efficiency improvement. Power-effcient cores can be paired with higher performance cores in an HMP to achieve a beneficial design in terms of both power and performance. However, such processors produce challenges in the effective mapping of threads to cores. An application could have(More)
A new dynamic vector approach for the selection and management of the configuration of a reconfigurable superscalar processor is proposed. This new method improves on previous work that used steering vectors to guide the selection of functional units to be loaded into the processor. Dependencies among instructions in the instruction buffer are analyzed to(More)
A design process is presented for the selection of a set of instruction set extensions for the PowerPC 405 processor that is embedded into the Xilinx Virtex family of FPGAs. The instruction set of the PowerPC 405 is extended by selecting additional instructions from the full 32-bit PowerPC instruction set architecture (ISA), of which the PowerPC 405 ISA is(More)
Short term traffic speed and volume prediction is an important component of well developed Intelligent Transportation Systems and Advanced Traveler Information Systems. In this paper, we examine the use of polled Remote Traffic Microwave Sensors as a data source for aggregate traffic predictors. Clock skew and data loss due to network transience pose(More)
We first discuss the curricular revisions required to implement " DSP First " in both the Electrical and Computer Engineering B.S. degrees at the University of Oklahoma. We follow this by describing our experiences over the past two years using this approach to education. We have noticed that students tend to select DSP projects in two digital systems(More)