Monika Vaishnav

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Despite abundant library resources for many organisms, physical mapping of these organisms has been seriously limited due to lack of efficient library screening techniques. We have developed a highly efficient strategy for large-scale screening of genomic libraries based on multiplex oligonucleotide hybridization on high-density genomic filters. We have(More)
We designed reconfigurable 8x8 multiplier architecture in 180nm with 1.8 power supply based on Wallace Tree, efficient in power and regularity without increase in delay and area. The idea is the generation of partial products in parallel using AND gates. The addition of partial products is reducing using Wallace Tree which is hierarchically divided into(More)
A 32 bit high speed area efficient Wallace tree multiplier is designed using verilog HDL and implemented in FPGA. The circuit is designed using carry save adder architecture and finally with one look ahead carry adder. The design is an improved version of tree based Wallace tree multiplier architecture. This paper aims at high speed multiplication and an(More)
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