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This paper presents a high-speed low-power 1-bit full adder cell designed upon an alternative logic structure to derive the SUM and CARRY outputs. Hspice and Nanosim simulations show that this full adder cell designed using a 0.35μm CMOS technology and supplied with 3.3V, exhibits delay and power dissipation around 720ps and 840μW, respectively.(More)
In this paper we present a new noise-tolerant dynamic circuit technique suitable for pipelined dynamic digital circuits. The effectiveness of this technique is demonstrated by means of HSPICE simulations for two kind of gates, CMOS AND and OR gates, both TSPC and Domino. In order to have a clear idea about this proposal's noise immunity improvement we(More)
Noise issues are becoming an important concern in digital systems due to the aggressive scaling trends in devices and interconnections. To address this problem a new noise-tolerant dynamic circuit technique suitable for dynamic logic styles is presented. Simulation results show that the proposed technique improves the ANTE by 3.4 and 2.8 over conventional(More)
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