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Several approaches have been proposed to accelerate the NP-complete Boolean Satisfiability problem (SAT) using reconfigurable computing. We present an FPGA based clause evaluator, where each clause is modeled as a shift register that is either right shifted, left shifted, or standstill according to whether the current assigned variable value satisfy,(More)
Several approaches have been proposed to accelerate the NP-complete Boolean Satisfiability problem (SAT) using reconfigurable computing. In this paper, we present a five-stage pipelined SAT solver. SAT solving is broken into five stages: variable decision, variable effect fetch, clause evaluation, conflict detection, and conflict analysis. The solver(More)
The Boolean satisfiability problem (SAT) is a central problem in artificial intelligence, mathematical logic and computing theory with wide range of practical applications. Being an NP-complete problem, the used SAT's solving algorithm execution time influences the performance of SAT-based applications. FPGAs represent a promising technology for(More)
A framework for TLM architecture exploration of multi-core systems is presented. Starting with a Task Precedence Graph (TPG) as a design entry, different architectures with different number of processor cores, number of busses, task-to-processor and channel-to-bus mappings are automatically generated. The viability and potential of the proposed approach is(More)
The Boolean satisfiability problem (SAT) is an NP-complete problem so software SAT's solving algorithm execution time influences the performance of SAT- based CAD tools. In this paper, we present a new approach for implementing conflict analysis based on a conflicting variables accumulator and priority encoder to determine backtrack level Using this(More)