Moira Miranda

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Nearly all platforms use a multi-layer memory hierarchy to bridge the enormous latency gap between the large off-chip memories and local register files. However, most of previous work on HW or SW controlled techniques for layer assignment have been mainly focussed on performance. As a result, the intermediate layers have been assigned too large sizes(More)
Scaling beyond the 90nm node is not automatically accompanied by a lower energy per function and a better performance. This is true both for transistors and interconnects. Since IC performance remains important in a competitive world, the success of scaled technologies are to be coupled with innovative circuit and system design strategies. Therefore, a much(More)
The implementation of advanced channel receivers using low-end though specialised instruction set media processors is very attractive because of design productivity and cost efficiency reasons. However, achieving real-time using these platforms is not a trivial task. In this paper, we illustrate the application of our Data Transfer and Storage Exploration(More)
Minimising the energy consumption due to the data storage and transfer in data-dominated systems is critical for the design of embedded systems. Distributed memory organisations have been proposed as an efficient storage architecture alternative. However, the impact of the interconnect overhead in these has been traditionally neglected, which is not(More)
The implementation of advanced channel receivers using low-end multimedia instruction set processors is a productive, flexible and cost effective alternative to custom hardware. The stringent real-time and low-power requirements become attainable on condition that for these applications the impact of the data transfer and storage related issues is first(More)
In this paper a comparative study on the use of extended and unscented Kalman filters for state estimation in nonlinear systems is presented. This is done to reveal the differences, and congruencies, in filters' synthesis in view of real plant implementation on embedded platforms. One of the objectives is to validate the usual performance measures of the(More)
This paper illustrates the strong interaction between background data format organization and foreground data in the context of speed and power efficient Sub-Word level Parallel (SWP) program generation. Such interaction, if not considered well, results in an (un)packing and reordering overhead that is typically required to match the format of data stored(More)
At nanometer nodes (e.g., 45nm and beyond), stochastic fluctuations on the implemented features and doping levels during the processing of devices is making the electrical parameters of wires and transistors to become more unpredictable, resulting in process variability. Designers cannot neglect the impact of variability on their designs any more, not only(More)
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