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Feedback-Based Energy Management in a Standby-Sparing Scheme for Hard Real-Time Systems
The interaction between fault tolerance and energy consumption is an interesting avenue in the realm of designing embedded systems. In this paper, a scheme for reducing energy consumption inExpand
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Exploring the Potential for Collaborative Data Compression and Hard-Error Tolerance in PCM Memories
Limited write endurance is the main obstacle standing in the way of using phase change memory (PCM) in future computing systems. While several wear-leveling and hard-error tolerant techniques haveExpand
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Cost-effective write disturbance mitigation techniques for advancing PCM density
Rapid technology scaling has enabled the integration of many cores into a single chip. Given this level of core integration, the requirements for a large and scalable main memory system will onlyExpand
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Two-State Checkpointing for Energy-Efficient Fault Tolerance in Hard Real-Time Systems
Checkpointing with rollback recovery is a well-established technique to tolerate transient faults. However, it incurs significant time and energy overheads, which go wasted in fault-free executionExpand
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DRVS: Power-efficient reliability management through Dynamic Redundancy and Voltage Scaling under variations
Many-core processors facilitate coarse-grained reliability by exploiting available cores for redundant multithreading. However, ensuring high reliability with reduced power consumption necessitatesExpand
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Simultaneous hardware and time redundancy with online task scheduling for low energy highly reliable standby-sparing system
Standby-sparing is one of the common techniques in order to design fault-tolerant safety-critical systems where the high level of reliability is needed. Recently, the minimization of energyExpand
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Adaptive Bandwidth Management for Performance-Temperature Trade-offs in Heterogeneous HMC+DDRx Memory
High fabrication cost per bit and thermal issues are the main reasons that prevent architects from using 3D-DRAM alone as the main memory. In this paper we address this issue by proposing aExpand
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Energy-efficient mapping of biomedical applications on domain-specific accelerator under process variation
The variability of deep-submicron technologies creates systems with asymmetric cores from a frequency and leakage power viewpoint, which makes an opportunity for performance-power optimization. InExpand
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dsReliM: Power-constrained reliability management in Dark-Silicon many-core chips under process variations
Due to the tight power envelope, in the future technology nodes it is envisaged that not all cores in a many-core chip can be simultaneously powered-on (at full performance level). The power-gatedExpand
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ElasticCore: Enabling dynamic heterogeneity with joint core and voltage/frequency scaling
Heterogeneous architectures have emerged as a promising solution to enhance energy-efficiency by allowing each application to run on a core that matches resource needs more closely than aExpand
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