Mohamed Lamine Berrandjia

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IC and SPI are the most commonly used serial protocols for both inter-chip and intra-chip low/medium bandwidth data-transfers. This paper contrasts and compares physical implementation aspects of the two protocols through a number of recent Xilinx’s FPGA families, showing up which protocol features are responsible of substantial area overhead. This valuable(More)
Optimizing the number of additions in constant coefficient multiplication is conjectured to be a NP-hard problem. In this paper, we report a new heuristic requiring an average of 29.10% and 10.61% less additions than the standard canonical signed digit representation (CSD) and the double base number system (DBNS), respectively, for 64-bit coefficients. The(More)
In embedded control applications, control-rate and energyconsumption are two critical design issues. This paper presents a series of highspeed and low-power finite-word-length PID controllers based on a new recursive multiplication algorithm. Compared to published results into the same conditions, savings of 431% and 20% are respectively obtained in terms(More)
In this paper, radix-2 arithmetic is explored to minimize the number of additions in the multiplication by a constant. We provide the formal proof that for an N-bit constant, the maximum number of additions using radix-2 is lower than Dimitrov’s estimated upper-bound (2.N/log(N)) using double base number system (DBNS). In comparison to canonical signed(More)
This paper addresses the problem of multiplication with large operand sizes (N≥32). We propose a new recursive recoding algorithm that shortens the critical path of the multiplier and reduces the hardware complexity of partial-product-generators as well. The new recoding algorithm provides an optimal space/time partitioning of the multiplier architecture(More)
ASIC or FPGA implementation of a finite wordlength PID controller requires a double expertise: in control system and hardware design. In this paper, we only focus on the hardware side of the problem. We show how to design configurable fixed-point PIDs to satisfy applications requiring minimal power consumption, or high control-rate, or both together. As(More)
This paper addresses the problem of multiplication with large operand sizes (N≥32). We propose a new recursive recoding algorithm that shortens the critical path of the multiplier and reduces the hardware complexity of partial-product-generators as well. The new recoding algorithm provides an optimal space/time partitioning of the multiplier(More)
In this paper, a new recursive multibit recoding multiplication algorithm is introduced. It provides a general space-time partitioning of the multiplication problem that not only enables a drastic reduction of the number of partial products (N/r), but also eliminates the need of pre-computing odd multiples of the multiplicand in higher radix (r≥3)(More)
ion Simplification of details, approximation of complex problems ADC Analog to Digital Converter AFM Atomic Force Microscopy ALU Arithmetic and Logic Unit ASIC Application Specific Integration Circuit Ath Adder Depth, the maximum number of serial adder-operations from input to output Avg Average number of additions BHM Bull Horrocks modified, an existing(More)