Mohamed El-Hadedy

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In this paper we describe in details the tweaked cryptographic hash function Edon-R that we denote as Edon-R′. Edon-R was submitted as a candidate for SHA-3 hash competition organized by National Institute of Standards and Technology (NIST). The difference between originally submitted version of Edon-R and version Edon-R′ is in the added(More)
This is the supporting documentation that describes in details the cryptographic hash function BLUE MIDNIGHT WISH which is submitted as a candidate for SHA-3 hash competition organized by National Institute of Standards and Technology (NIST), according to the public call [1]. BLUE MIDNIGHT WISH is a cryptographic hash function with output size of n bits(More)
This is the first implementation in FPGA of the recently published class of public key algorithms - MQQ, that are based on quasigroup string transformations. Our implementation achieves decryption throughput of 399 Mbps on an Xilinx Virtex-5 FPGA that is running on 249.4 MHz. The encryption throughput of our implementation achieves 44.27 Gbps on an Xilinx(More)
This paper presents the design and analysis of an area efficient Blue Midnight Wish compression function with digest size of 256 bits (BMW-256) on FPGA platforms. The proposed architecture achieves significant improvements in system throughput with reduced area. We demonstrate the performance of the proposed BMW hash function core using VIRTEX 5 FPGA(More)
Many electronic content providers today like Flickr and Google, offer space to users to publish their electronic media(e.g. photos and videos) in their cloud infrastructures so that they can be publicly accessed. Features like including other information, such as keywords or owner information into the digital material is already offered by existing(More)
This paper presents the design and analysis of an area efficient implementation of the SHA-3 candidate Blue Midnight Wish (BMW-256) hash function with digest size of 256 bits on an FPGA platform. Our architecture is based on a 32 bit data-path. The core functionality with finalization implementation without padding stage of BMW on Xilinx Virtex-5 FPGA(More)