Mohamad Hairol Jabbar

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In this paper, we describe the architecture and implementation of 3D multiprocessor with 3D NoC. The 2 tiers design is based on 16 processors communicating using a 4x2 mesh NoC and will be fabricated using Tezzaron technology with 130 nm Global Foundaries low power standard library. Due to the limitation when investigating NoC performance using simulation,(More)
— The aim of this paper is to discuss the optimization of the hardware description language (HDL) design using fixed-point optimization and speed optimization through a pipelining method. This optimization is very crucial to achieve the best performance in terms of speed, area and power consumption of the generated HDL code before deploying the field(More)
3D integration is one of the feasible technologies for producing advanced computing architecture to support ever-increasing demand of higher performance computing especially in mobile devices. The emerging trend of multiprocessor architecture has made Network on Chip (NoC) architecture the best solution for future manycore architecture devices. In this(More)
The need for higher performance devices to enable more complex applications continues to drive the growth of electronic design especially in the mobile markets. 3D integration is one of the feasible technologies to increase the system's performance and device integration by stacking multiple dies interconnected using through silicon vias (TSV). NoC-based(More)
Nowadays, wireless technology has been widely used in various applications. Mobile Internet users have been increasing rapidly around the world. Several benefi ts of using mobile internet includes transmitting data through querying and updating databases, e-commerce transactions and daily business application as well as in education such querying(More)
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