Mohab H. Anis

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A new contention-free Domino logic (CF-Domino) that is especially suited for low threshold voltage (LVT) is reported. Its superior noise margin and speed over conventional Domino circuits for LVTs are demonstrated using HSPICE simulations and a 0.25pm CMOS technology with a supply voltage of 2.5V. The impacts of the new technique on dynamic and leakage(More)
As VLSI technology pushes into advanced nodes, designers and foundries have exposed a hitherto insignificant set of yield problems. To combat yield failures, the semiconductor industry has deployed new tools and methodologies commonly referred to as design for manufacturing (DFM). Most of the early DFM efforts concentrated on catastrophic failures, or(More)
Due to the limitation in speed and throughput of the traditional Von Neumann architecture, the interest in braininspired neuromorphic systems has been the focus of recent research activities. RRAM device has been extensively used as synapses in neuromorphic systems due to its many advantages including small size and compatibility with CMOS fabrication(More)
With continuous and aggressive technology scaling, suppressing the stand-by power is among the top priorities for SRAM design. Switching off the less-frequently accessed blocks is an efficient way to reduce the stand-by power, provided that the information stored in these blocks can be restored. Non-volatile memories (NVMs) are integrated into SRAM cells to(More)
Better than worst-case (BWC) design is an design emerging paradigm in which the conservative frequency guardbands used in conventional designs are removed at the expense of introducing a a non-zero (but small) error probability. A fundamental challenge in the design of better-than-worst-case circuits is to devise scalable and accurate techniques for(More)