Misao Miyata

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The architecture of the TX3 implementation of the TRON-CHIP32 specification is discussed. TX3 supports the full instruction set, including the decimal, floating-point, and other complex instructions. Average performance above 10-MIPS is expected. This performance level is obtained by the use of an 8-kB instruction cache, 8-kB data cache, decoded instruction(More)
A description is given of the architecture of the TX1, which is the first 32-bit microprocessor of the Toshiba TX series. The TX1 supports 92 instructions including high-level instructions for efficient use of compilers and operating systems. The effectiveness of the high-level instructions was evaluated by comparing their execution cycles on the TX1 board(More)
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