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- Miroslav N. Velev, Randal E. Bryant
- Proceedings 37th Design Automation Conference
- 2000

We extend the Burch and Dill flushing technique [6] for formal verification of microprocessors to be applicable to designs where the functional units and memories have multicycle and possibly… (More)

- Miroslav N. Velev, Randal E. Bryant
- CHARME
- 1999

We present a collection of ideas that allows the pipeline verification method pioneered by Burch and Dill [5] to scale very efficiently to dual-issue superscalar processors. We achieve a significant… (More)

- Miroslav N. Velev, Randal E. Bryant
- Proceedings of the 38th Design Automation…
- 2001

We compare SAT-checkers and decision diagrams on the evaluation of Boolean formulas produced in the formal verification of both correct and buggy versions of superscalar and VLIW microprocessors. We… (More)

We present a method for translating Boolean formulas to CNF by identifying gates with fanout count of 1, and merging them with their fanout gate to generate a single set of equivalent CNF clauses.… (More)

- Miroslav N. Velev
- IEEE/ACM International Conference on Computer…
- 2007

Many important EDA problems can be formulated as graph coloring, which is a class of the Constraint Satisfaction Problem (CSP). This paper makes three contributions. First, we define new encodings… (More)

In using the logic of equality with unininterpreted functions to verify hardware systems, specific characteristics of the formula describing the correctness condition can be exploited when deciding… (More)

- Miroslav N. Velev
- Proceedings Design, Automation and Test in Europe…
- 2004

The paper presents a method for translating Boolean circuits to CNF by identifying trees of ITE operators, where each ITE has fanout count of 1, and representing every such tree with a single set of… (More)

- Miroslav N. Velev, Randal E. Bryant
- CAV
- 2001

The property of Positive Equality [2] dramatically speeds up validity checking of formulas in the logic of Equality with Uninterpreted Functions and Memories (EUFM) [4]. The logic expresses… (More)

- Randal E. Bryant, Steven M. German, Miroslav N. Velev
- ACM Trans. Comput. Log.
- 1999

The logic of Equality with Uninterpreted Functions (EUF) provides a means of abstracting the manipulation of data by a processor when verifying the correctness of its control logic. By reducing… (More)

- Miroslav N. Velev, Randal E. Bryant
- IJES
- 2005

We present a tool flow for high-level design and formal verification of embedded processors. The tool flow consists of the term-level symbolic simulator TLSim, the decision procedure EVC (Equality… (More)