Mirko Prezioso

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Despite much progress in semiconductor integrated circuit technology, the extreme complexity of the human cerebral cortex, with its approximately 10(14) synapses, makes the hardware implementation of neuromorphic networks with a comparable number of devices exceptionally challenging. To provide comparable complexity while operating much faster and with(More)
Information and communication technology (ICT) is now calling for solutions enabling lower power consumption, further miniaturization, and multifunctionality requiring the development of new device concepts and new materials. [ 1 ] One of the most fertile approaches to meet such demands is spintronics, which is now facing the challenge of evolving from the(More)
Nanoparticles (NPs) embedded in a conductive or insulating matrix play a key role in memristors and in flash memory devices. However, the role of proximity to the interface of isolated NPs has never been directly observed nor fully understood. Here we show that a reversible local switching in tunnel conductivity can be achieved by applying an appropriate(More)
We have fabricated and successfully tested an analog vector-by-matrix multiplier, based on redesigned 10x12 arrays of 55 nm commercial NOR flash memory cells. The modified arrays enable high-precision individual analog tuning of each cell, with sub-1% accuracy, while keeping the highly optimized cells, with their long-term state retention, intact. The array(More)
We have designed, fabricated, and successfully tested a prototype mixed-signal, 28×28-binary-input, 10-ouput, 3-layer neuromorphic network (" MLP perceptron "). It is based on embedded nonvolatile floating-gate cell arrays redesigned from a commercial 180-nm NOR flash memory. The arrays allow precise (~1%) individual tuning of all memory cells, having(More)
The rapidly expanding hardware-intrinsic security primitives are aimed at addressing significant security challenges of a massively interconnected world in the age of information technology. The main idea of such primitives is to employ instance-specific process-induced variations in electronic hardware as a source of cryptographic data. Among the emergent(More)
We experimentally demonstrate classification of 4x4 binary images into 4 classes, using a 3-layer mixed-signal neuromorphic network ("MLP perceptron"), based on two passive 20x20 memristive crossbar arrays, board-integrated with discrete CMOS components. The network features 10 hidden-layer and 4 output-layer analog CMOS neurons and 428 metal-oxide(More)