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Welcome to the special issue on field programmable gate arrays (FPGAs). FPGAs are becoming an increasingly important part of embedded systems, as the collection of papers in this issue illustrates. " An overview of reconfigurable hardware in embedded systems " provides a comprehensive overview of the state-of-the-art use of reconfigurable hardware in(More)
We present a parameterized floating-point library for use with reconfigurable hardware. Our format is both general and flexible. All IEEE formats are a subset of our format, as are all previously published floating-point formats for reconfigurable hardware. We have developed a library of fully parameterized hardware modules for format control, arithmetic(More)
Theorem proving techniques are particularly well suited for reasoning about arithmetic above the bit level and for relating diierent levels of abstraction. In this paper we show h o w a non-restoring integer square root algorithm can be transformed to a very eecient hardware implementation. The top level is a Standard ML function that operates on unbounded(More)
We have implemented a two-dimensional systolic array QR decomposition on a Xilinx Virtex5 FPGA using the Givens rotation algorithm. QR decomposition is a key step in many DSP applications including sonar beamforming, channel equalization, and 3G wireless communication. Compared to previous work that implements Givens rotations using a one-dimensional(More)
In mapping the k-means algorithm to FPGA hardware, we examined algorithm level transforms that dramatically increased the achievable parallelism. We apply the k-means algorithm to multi-spectral and hyper-spectral images, which have tens to hundreds of channels per pixel of data. K-means is an iterative algorithm that assigns assigns to each pixel a label(More)